1. Field of the Invention
This invention relates to SRAM cells and more particularly to word lines and interconnection lines therefor.
2. Description of Related Art
U.S. Pat. No. 4,980,732 of Okazawa "Semiconductor Device Having an Improved Thin Film Transistor" shows an SRAM with a TFT load.
U.S. Pat. No. 5,155,055 of Gill et al "Method of Making an Electrically-Erasable Electrically Programmable Read-Only Memory Cell with Self-Aligned Tunnel" describes at Col. 3, lines 36, et seq. the use of "bitlines 13 formed beneath thick thermal silicon layers 14 in the face" of the substrate in an array of EPROMs. "These buried bitlines 13 form the source region 15 and the drain region 16 for each of the cells 10." Referring to the Abstract of the patent, it states "the bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance."
FIGS. 1A AND 1B show two different prior art SRAM configurations which illustrate certain problems in the prior art which will be explained below.
FIG. 1A shows a conventional cell with active layer structures 93, 94 and 96, etc. on top of which polysilicon line 95, polysilicon interconnection line I.sub.2 and wordline 97 have been formed. A transistor TPA is formed between active structure 96 and polysilicon line 95. A node N1 is formed between structure 93 and polysilicon line 95. Node N2 connects between structure 96 and line I.sub.2. Transistor TPB lies at the intersection of line I.sub.2 and structure 93. Node N1 is formed at the other end of line 95 and the intermediate section of structure 93. Transistor T1 is formed at the intersection of structure 93 and wordline 97. The portion of structure 93 between transistor TPB and transistor T1 is the interconnection line I.sub.1 formed of active layer material. At the other end of wordline 97, a transistor T2 is at the intersection with structure 94.
FIG. 1B shows a split wordline cell with active layer structures 90, 91, etc. on top of which polysilicon lines N1 and N2 and wordlines WL1 and WL2 are formed. Transistor T1 is at the intersection of line N1 and structure 90. Transistor T2 is at the intersection of line N2 and structure 91. Transistor T3 is at the intersection of line WL1 and structure 90. Transistor T4 is at the intersection of structure 91 and word line WL2.
For the EPROM or ROM buried N+ is used for bit lines for long distance connections. But SRAM bit lines are always defined by metal. An object of this invention is to provide an SRAM employing a buried N+ line for local interconnection lines connected from, for example, the Junction in FIG. 2 between the drains of transistors T4 and T2 to the gate of transistor T1. It is also an object of this invention to locate the pulldown transistors T1 and T2 on opposite sides of the wordline, so local interconnection line I.sub.1 and local interconnection line I.sub.2 are defined by the buried N+ lines.
Heretofore, as seen in the plan views shown in FIGS. 1A and 1B, pulldown transistors such as transistor TPA and transistor TPB in FIG. 1A and transistor T1 and transistor T2 in FIG. 1B have been located on the same side of the word line. Local interconnection line I.sub.1 and local interconnection line I.sub.2 have been defined by two different conductors (one by N+ diffusion I.sub.1, the other by polysilicon I.sub.2 in FIG. 1A. FIG. 1B shows two N+ diffusion local interconnection line regions I.sub.1 (diffusion 90) and I.sub.2 (diffusion 91) and a buried contact, however they still need two word lines WL1 and WL2. The concept of employing the layout of the instant invention had not been contemplated in the prior art designs.
For a conventional SRAM cell (FIG. 1A) interconnection of two nodes, an N+ diffusion 93 and polysilicon I.sub.2 are used. Active diffused regions and polysilicon have different resistance values so such an SRAM cell is asymmetric in the sense that the resistance of polysilicon and the N+ diffusion are different and the distances along the lines are different.
Some symmetric cells need two word lines WL1 and WL2 as in FIG. 1B. See IEDM 91-477. An object of this invention and a significant advantage of this invention is to use only one word line.
FIG. 1A shows a prior art conventional SRAM cell. The features of the cell are that the local interconnection line I.sub.1 and local interconnection line I.sub.2 are defined in two different layers (the first is a diffusion of an N+ diffusion and the other layer is a polysilicon deposit.) The resistor materials are different and the cell is more unstable because the resistor N1 and N2 are different, so the currents of transistor T1 and transistor T2 are different. Since the cell prefers for the higher current transistor to turn on, this cell is asymmetric.
The advantage of the conventional cell is that the cell size is small. The disadvantages are as follows:
1) that they are asymmetric with a 45.degree. layout (resolution in SHRINK (Super High Resolution Illumi-Nation Control) or lithography or the phase shift mask is not good at 45.degree.), and PA1 2) the metal rule is tight. PA1 1) that the cell size is large, PA1 2) the metal rule is tight and the timing does not match. PA1 a) a substrate comprising a semiconductor material, PA1 b) a pair of local interconnection lines in the silicon substrate, PA1 c) a word line on the surface of the device, PA1 d) a source region and drain region formed in the substrate Juxtaposed with the buried local interconnection line, PA1 e) a layer of gate oxide above the source region and drain region, PA1 f) a gate above the gate oxide Juxtaposed with the source region and drain region, and PA1 g) a pair of pull down transistors located on opposite sides of said wordline, PA1 a) forming a base oxide on a semiconductor substrate, PA1 b) forming a FOX structure on the surface of the base oxide and the semiconductor substrate, PA1 c) implanting a pair of buried local interconnection lines into the substrate, PA1 d) applying polysilicon and etching with a mask, and PA1 e) forming source region and drain region in the substrate. PA1 a) forming a field oxide structure on the surface of a semiconductor substrate, PA1 b) implanting a pair of buried local interconnection lines into the substrate, PA1 c) forming a gate polysilicon structure on the substrate, PA1 d) forming a mask and etching the polysilicon to form gates, and PA1 e) forming source region and drain region in the substrate.
The local interconnection line I.sub.1 and local interconnection line I.sub.2 are in different layers (diffusion 93 and polysilicon node N2.) (See FIG. 1A.) There is one word line WL (polysilicon.) The pull down transistor T.sub.PA is on the same side of the word line WL as the local interconnection lines.
FIG. 1B shows a prior art split wordline cell with wordline WL1 the local interconnection line I.sub.1 and the local interconnection line I.sub.2 can be defined in the same layer (diffusion) but that design requires two word lines WL1 and WL2 so the cell size is larger and timing of pass transistors T3 and T4 may not match because for the SRAM the pass gate transistors T3 and T4 must turn on at the same time for SRAM sensing in a differential amplifier to differentiate two bit lines.
The advantage of the split wordline cell is that the cell size is symmetric, and that there is no 45.degree. layout. The disadvantages are as follows:
The local interconnection lines are in the same layer (diffusion) as can be seen by reference to FIG. 1B. There are two word lines WL1 and WL2 composed of polysilicon (from the first polysilicon layer,) as shown in FIG. 1B.
The pull down transistors T1 and T2 are on the same side of the word line WL1 as in the case of the conventional SRAM above.
An object of this invention is to provide an SRAM with the interconnections in the same layer, preferably formed of a buried N+ dopant.
A further object of this invention mentioned above is to provide an SRAM with one wordline, preferably formed of polysilicon.
Still another object of this invention is to provide a pull down transistor on the opposite side of the word line.
A significant object of this invention is to provide a symmetrical SRAM with a small cell size.
A further object of this invention is cell current ratio pull down transistor/pass transistor is high because the cell is not limited by this rule.
An object of this invention is to avoid a 45.degree. layout.
An important object of this invention is to provide a loose metal rule.